1. Field of the Invention
This invention relates to the field of integrated circuits. More particularly, this invention relates to the communication of diagnostic signals to or from an integrated circuit.
2. Description of the Prior Art
It is known to provide integrated circuits with on-chip diagnostic capabilities. These capabilities can include debug, trace, calibration, configuration, production test and/or in-circuit programming. As integrated circuits increase in complexity such that more and more functional components are included in an ever decreasing circuit area, the provision of on-chip diagnostic mechanisms becomes increasingly useful and important.
A problem arising with integrated circuits is associated with limitations imposed by the integrated circuit packaging (due to ever decreasing circuit area) upon the number of integrated circuit pins provided. The increasing complexity of functional components of integrated circuits gives rise to a corresponding increase in the required number of circuit pins for communicating signals to and from the integrated circuit during normal operation. However, it is difficult to increase the number of pins provided on the circuit given that space is limited.
Integrated circuits typically generate large amounts of diagnostic information such as trace information. This diagnostic information is typically sent off-chip for processing. On-chip trace buffers can store small amounts of trace information and/or help smooth out trace data peaks generated by the integrated circuit. Furthermore, the trace information can be compressed to help reduce the bandwidth requirements. However, despite the provision of trace data buffering and trace data compression the amount of trace data that is generated can still be very large.
A known technique for communicating diagnostic signals to and from an integrated circuit is to provide dedicated trace and/or debug pins on the integrated circuit package through which the diagnostic signals may pass. One example of such an arrangement would be the Test Access Port pins associated with JTAG debug.
Typically a 1 to 32-bit bus is provided to communicate trace information and at a typical 100 MHz operating speed these buses provide between 12.5 MB/s and 400 MB/s of bandwidth respectively. The additional circuit pins required for communication of this diagnostic data increase the silicon area of the integrated circuit and thus increase the area of the integrated circuit, the size and number of pins of the package and thus increase the silicon and package cost.
One characteristic of diagnostic signals associated with an integrated circuit are that they may be used for only a small proportion of the life of the device. For example, debug capabilities may in practice only be required for debugging a few prototype devices and production devices will not use the debug capabilities provided on-chip. Thus the trace pins may only be bonded out in prototype designs. Another example is integrated circuit calibration, configuration, or in-circuit programming, which normally takes place upon integrated circuit fabrication and manufacture and does not form part of the ongoing functional use of the integrated circuit by a user. The present technique recognises that provision of dedicated diagnostic interfaces comprising one or more integrated circuit pins is wasteful of resources.
The following documents describe known ways of handling diagnostic data on an integrated circuit. These documents are accessible via the website www.googlescholar.com
“System Solutions for a Baseband SoC,” by Dominic Pajak, Processors Division, ARM, IQ (Information Quarterly) Magazine, Volume 5, Number 2, 2006;
“Processor and System Bus On Chip Instrumentation” by Rick Leatherman, Bruce Ableidinger et al, by First Silicon Solutions (www.fs2.com);
“Debugging Aids for System-on-a-Chip” by Ross Bannatyne, 0-7g03-5075-8/98/01998 IEEE;
“Design for Debug: Catching Design Errors in Digital Chips” by Bart Vermeulen et al 0740-7475/02/2002 IEEE;
“Embedded Test and Debug of Full Custom and Synthesisable Microprocessor Cores” by Andrew Burdass et al, White paper available from www.arm.com;
“Debug architecture for System on Chip taking full advantage of the Test Access Port” by E Moerman et al Proceedings of the Eighth IEEE European Test Workshop (ETW'03)1530-1877/03 2003 IEEE;
Nexus interface Application Note AN2298/D by Randy Dees available from the website www.freescale.com; and
Digital System Debug Techniques by Mark W Klingensmith, 0-7803-4303-4/97/0.0109 97 IEEE.